1. Field of the Invention
This invention generally relates to electronic circuitry and, more particularly, to a Traveling Pulse Wave Quantizer.
2. Description of the Related Art
FIGS. 1A and 1B are, respectively, a schematic diagram of a Vernier delay line (VDL) based time-to-digital converter (TDC), and an associated timing diagram (prior art). A VDL TDC is a popular choice for applications that require fine time resolution. It is based on the use of two parallel tapped delay lines, one fed with reference (start) pulses and the other line with signal (stop) pulses. The fast delay line that is used for the signal pulses is constructed or tuned to be slightly faster than the reference slow delay line. The edge of a start (reference) pulse, occurring before the stop signal pulse edge, is used as a reference, travelling along the slow delay line. The stop signal edge arrives later and propagates along the fast delay line, eventually catching up with the start (reference) edge travelling on the parallel slow delay line. The location along the delay line where the pulses coincide corresponds to the time difference between the start (reference) pulse edge and the stop signal edge. As the time resolution is set by the delta of two unit delays, as opposed to a full unit delay, it can be made almost arbitrarily fine.
The location of the edge crossing is captured by a sampler constructed from a bank of D-flip flops. The flip flops are clocked by the pulses from the reference (slow) delay line taps and the D-inputs are connected to the corresponding taps in the signal (fast) delay line. Once the two edges have passed through the entire delay line(s), the digital value corresponding to the delay difference is available as a thermometer coded digital word at the output of the sampler flip-flop bank. This signal is captured by the system clock and converted to a binary format. Alternatively the thermometer-to-binary conversion can be performed before capturing the signal with the system clock. Either way, the throughput of the VDL TDC is limited by the total length (in time) of the delay line as the stop signal and start (reference) edges need to pass through the entire delay line before the next pair of edges can be fed in. If a new stop pulse is fed in before the previous thermometer coded output is captured, the result is a corrupted digital signal. For proper operation the following condition has to be met: Tclk>Tdel, where Tclk is the clock period and Tdel the combined delay of all the delay elements in the slow delay line.
It would be advantageous if a VDL TDC could be structured so that more than one start pulse could be processed simultaneously.